Field effect semiconductor device having an unsaturated triode vacuum tube characteristic

ABSTRACT

A field effect transistor comprises a semiconductor channel, a source and a drain electrode formed at the opposite ends of the channel and a gate electrode provided on the side of the channel. The channel has a small impurity density and therefore the depletion layer extending from the gate goes deep into the channel to substantially close the conductive portion of the channel even in the absence of a gate voltage. The drain current will not flow where the drain voltage is below a certain threshold voltage, and will flow where the drain .[.volage.]. .Iadd.voltage .Iaddend.is above the threshold voltage exhibiting a .Iadd.substantially .Iaddend.linear resistance characteristic. This drain-current to drain-voltage characteristic simulates the anode-current to anode-voltage characteristic of the triode vacuum tube very closely.

BACKGROUND OF THE INVENTION

1. Field of the Invention:

This invention relates to a field effect transistor, and moreparticularly to a field effect transistor having a drain-current todrain-voltage characteristic similar to the anode-current toanode-voltage characteristic of the triode vacuum tube.

2. Description of the Prior Art:

There are two types in field effect transistors (FET's), i.e., ametal-oxide-semiconductor (MOS) type and a junction-gate (JUG) type. Inboth cases, the current of the carriers (unipolar) flowing from thesource to the drain is effectively controlled by the gate voltage. Thegate voltages applied with respect to the source voltage works tocontrol the height of the depletion layer extending from the gate intothe channel, which in turn controls the height of the region throughwhich a current is allowed to flow. In a MOS FET, the current flowingthrough the channel formed beneath the gate electrode and insulated fromthe gate electrode by an oxide layer is controlled by the electric fieldestablished in the channel by the gate voltage. This is due to thevariation in the height of the depletion layer extending from theoxide-semiconductor contact. In a JUG FET, a depletion layer formedaround the PN junction is varied by the gate voltage and controls thecurrent flowing through the channel. In conventional FET's of the bothtypes, it is arranged that the current channel is open (conductive) whenno gate voltage is applied externally and the conducting channel heightis varied by the applied gate voltage.

The present inventors have found that various advantages can be obtainedby forming an FET in such a fashion that the depletion layers (spacecharged layers) extending from the gates are substantially contiguous toeach other even when no gate voltage is applied. This will be firstdescribed referring to a junction type FET proposed in Japanese Pat.application No. 28405/1971 by one of the present inventors, which hastriode-like characteristics (unsaturated type) unlike the conventionalcurrent saturation type characteristics, and has a reduced series(source to drain) resistance so that the product of the seriesresistance r_(s) (this forms a factor for generating negative feedback)and the transconductance G_(m) is suppressed substantially less thanunity.

A typical example of the characteristic curves is shown in FIG. 1, and aschematically illustrated structure which produces the characteristicsof FIG. 1 is shown in FIG. 2. Namely, when the gate voltage is absent orsmall, the drain current I_(D) increases almost linearly with increasingthe drain voltage V_(D), as is illustrated by curves 1, 2, and 3. Thismay be called resistance modulation, since the variation in the gatevoltage results in a variation in the resistance between the source andthe drain i.e., δV_(D) /δI_(D). When the negative gate voltage isincreased in magnitude to suppress the drain current I_(D), the draincurrent I_(D) first does not begin to flow until the drain voltage V_(D)reaches a certain value, and then above said certain value rapidlyincreases more than linearly with increasing drain voltage V_(D) as isshown by curves 4, 5, and 6. The phenomenon .[.that.]. .Iadd.whereby.Iaddend.the drain current I_(D) increases linearly with increasingvoltage V_(D) as is shown by curves 1, 2 and 3 mainly appears in thecase where the depletion layers extending from the gate electrodes G andG' .[.does.]. .Iadd.do .Iaddend.not .Iadd.yet .Iaddend.touch .[.yet.].each other, whereas the phenomenon that the drain current I_(D) .[.do.]..Iadd.does .Iaddend.not begin to flow until the drain voltage V_(D)reaches a certain positive value and increases rapidly with increasingdrain voltage V_(D) above said certain value mainly appears when thedepletion layers extending from the gates have grown large enough by theapplication of a gate voltage and touch (not touch, to say exactly, butbecome very close) each other. In the latter case, the applied drainvoltage below the certain value is found to be used for decreasing thepotential barrier of the pinch-off portion made in the current path bythe depletion layers.

In the above example, linear characteristics as shown by curves 1, 2,and 3 appeared when the gate voltage was small in magnitude, andcharacteristics very closely resembling those of a triode vacuum tube asshown by curves 4, 5, and 6 appeared when the gate voltage exceeded acertain value. Further, .Iadd.it is desirable that .Iaddend.the valueδV_(D) /δV_(G), which corresponds to the amplification factor μ of thetriode vacuum tube, .[.is desired to.]. be large for obtaining a fieldeffect transistor of a superior efficiency. Thus, it is desired torealize the characteristics corresponding to curves 4, 5, and 6 even inthe region of small gate voltage, or in other words without theaccompany of the characteristics corresponding to curves 1, 2, and 3,for providing elements of superior characteristics of a good efficiencyand of little distortion.

It has been found by the present inventors that the above requirementcan be satisfied by forming an FET in such a manner that the depletionlayers extending from the gate electrodes are substantially contiguous(very close but not integrally connected) to each other even when nogate voltage is applied.

This can be achieved by using depletion layers due to carrierdiffusion-recombination across a PN junction. Namely, the extent of adepletion .[.layers.]. .Iadd.layer .Iaddend.across the PN junction isdetermined by the barrier potential (or contact potential) and theimpurity concentration (density) in the crystal. Practically, if theresistivity of the semiconductor crystal substrate is known, an FEThaving such depletion layers which are formed only by the carrierdiffusion-recombination and are contiguous to each other even when nogate voltage is applied can be formed by appropriately selecting thedistance between the gate electrodes G and G'. In such a structure,since the depletion layers almost touch each other, the drain currentI_(D) can easily show triode-like characteristics, not showing linearincrease of the drain current with increasing drain voltage, evenwithout the application of a large negative gate voltage V_(G). Namely,characteristics as shown in FIG. 3 are obtained with a reduction orabsence of the linear region indicated by curves 1, 2, and 3 in FIG. 1.These transistors have such advantages that sufficient function can beobtained with a small gate voltage, that a large variation in the drainvoltage V_(D) can be obtained by a small variation in the gate voltageV_(G), and that excellent action with less distortion can be performed.In addition to these advantages, capacitances between gate-and-source,and gate-and-drain are reduced and the frequency characteristics areimproved.

The above description has been made on a transistor having a reducedseries resistance, but it also holds for a conventional transistorhaving a large series resistance. A conventional FET having a largeseries resistance and showing pentode-like characteristics can beconsidered as the above-mentioned FET having a reduced series resistanceand showing triode-like characteristics, itself, but now .[.providewih.]. .Iadd.provided with .Iaddend.a negative feed back circuit, or in.[.another word,.]. .Iadd.other words, .Iaddend.the FET .[.operating.]..Iadd.operates .Iaddend.in an emitter follower fashion. Therefore, theadvantages of the present concept described above can be also applied tosuch kind of transistors.

Next, description will be made on the state in which the depletionlayers respectively extending from the gates touch each other. As isdescribed above, the height of the depletion layer is a function of thebarrier potential at the junction or contact and the impurityconcentration (density) in the crystal. Usually, the height of adepletion layer is calculated by assuming that no carriers exist in thedepletion layer and that only space charges which are perfectly ionizedexist in the depletion layer and solving the Poisson's equation.

For example, in a case where a plate shaped PN junction has a stepwisecarrier concentration distribution, i.e. the carrier concentration onone side of the PN junction is far larger than that on the other side,so that a depletion layer grows only into the other side, the height ofthe depletion layer α is expressed by

    α=R√ V/N.sub.b

where R is a factor dependent on the physical constants of thesemiconductor, N_(b) the impurity concentration (density) in thesemiconductor on that side in which the depletion layer grows, and V theapplied voltage including the barrier potential. Strictly speaking, itis not that there are no carriers at all in the depletion layer, northat a clear boundary exists at the edge of the depletion layer betweenthe perfectly ionized region and the non-ionized region. Carriers aredistributed according to the Fermi-Dirac distribution even into adepletion layer. The effective extent of a depletion layer is at leastthree times larger than the width of the depletion layer α calculated asabove assuming that the depletion layer is perfectly ionized. Namely,the calculated height of the depletion layer based on the perfectionization assumption is much lower than the actual effective height.Therefore, even if such semi-conductor materials in which thecalculation with the perfect ionization assumption tells that thedepletion layers touch each other only by the barrier potential with agate-to-gate distance set at 20 micrometers is employed, the actualdepletion layers can touch (become very close .Iadd.to.Iaddend.) eachother with the gate-to-gate distance set at about 60 micrometers.

SUMMARY OF THE INVENTION

An object of the invention is to provide a field effect transistorhaving triode vacuum-tube-like characteristics.

Another object of the invention is to provide a field effect transistorcomprising a semiconductor substrate including a current channel, asource and a drain electrode, and gate electrodes sandwiching thecurrent channel, the depletion layers extending into the channel fromthe gate electrodes being substantially contiguous to each other even inthe absence of a gate voltage.

A further object of the invention is to provide a field effecttransistor comprising a semiconductor substrate including a currentchannel of a low carrier concentration (density) and gate regions of ahigh carrier concentration, a source and a drain electrode formed on thesemiconductor substrate at the both ends of the current channel, andgate electrodes formed on said gate regions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a graphical chart showing the drain-current to drain-voltagecharacteristics of a field effect transistor of non-saturated currenttype;

FIG. 2 is a schematic cross sectional view of a field effect transistorhaving the characteristics as shown in FIG. 1;

FIG. 3 is a graphical chart showing the drain-current to drain-voltagecharacteristics of a field effect transistor according to the presentinvention;

FIG. 4 is a schematic cross sectional view of a junction type fieldeffect transistor according to this invention;

FIGS. 5A and 5B are schematic perspective and schematic cross sectionalviews respectively of another embodiment of a junction type field effecttransistor according to the invention;

FIGS. 6A and 6B are schematic perspective and partial cross sectionalviews, respectively, of a further embodiment of a junction type fieldeffect transistor according to the invention;

FIGS. 7 and 8 illustrate further embodiments of junction type fieldeffect transistors of high output power according to the invention; and

FIGS. 9 to 11 are cross sectional views of embodiments of MOS type fieldeffect transistors according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Now, this invention will be described on the preferred embodimentsreferring to the accompanying drawings. Throughout the figuresillustrating the embodiments of the invention, the gate voltage is setat zero unless particularly specified.

A silicon FET is shown in FIG. 4 for illustrating the height of thedepletion layer. In a semiconductor substrate, gate electrode regionsindicated by .Iadd.a .Iaddend.hatched area are formed. Provided that theimpurity concentration (density) in the gate regions is far larger thanthat in the channel region and that the impurity concentration in thechannel region is uniformly distributed, the voltage V between thechannel region and the gate region when the depletion layers extendingfrom the gate regions touch each other is expressed by the equation

    V=.sub.q N.sub.B /2ε · α.sup.2

on the basis of the assumption of perfect ionization, where q is theelectron charge, N_(B) the impurity concentration in the channel region,ε the dielectric constant of the semi-conductor, and a the height of thedepletion layer (in this case, equal to α half of the gate-to-gatedistance). When no gate voltage is applied, the voltage V is entirelyformed by the contact potential (i.e., the barrier potential). Assumingthat this contact potential is 0.6 volt, the maximum half distance αbetween the gates becomes about 9, 3, and 0.9 micrometer(s) for theimpurity concentrations N_(B) of 10¹³ /cm³, 10¹⁴ /cm³, and 10¹⁵ /cm³respectively. Since these values are calculated on the assumption ofperfect ionization, the actual maximum distances between the gates G andG' (two times the height of a depletion layer) become approximately18×3, 6×3, and 1.8×3 micrometers for the semiconductors having animpurity concentration of 10¹³ /cm³, 10¹⁴ /cm³, and 10¹⁵ /cm²respectively.

FIGS. 5A and 5B show an embodiment of a junction-gate type FET having acircular transverse cross section. An annular gate is provided in theperiphery of a cylindrical semiconductor body. In this case, the voltageV when the depletion layer touches itself and closes the current path isexpressed by

    V=.sub.q N.sub.B /4ε · r.sub.a.sup.2

on the assumption of perfect ionization, where r_(a) is the radius ofthe annular gate. Actually, since the width of a depletion layer isabout three times as large as the calculated value, the depletion layerbecomes contiguous when the radius r_(a) is about √2×9×3, √2×3×3, and√2×0.9×3 micrometers for the impurity concentration N_(B) of 10¹³ /cm³,10¹⁴ /cm³, and 10¹⁵ /cm³, respectively.

A further embodiment of a junction-gate type FET is shown in FIGS. 6Aand 6B, in which a plurality of cylindrical gate regions are formed on aline with an interval of 2d. The pinch-off voltage in this case takes alittle more complicated form and is expressed as

    V=.sub.q N.sub.B /4εd.sup.2 (2 ln d/r.sub.3 +r.sub.j.sup.2 /d.sup.2 -l),

where r_(j) indicates the radius of one cylindrical gate region. At theinterval about three times as large as the interval 2d calculated fromthe above equation, the depletion layer can be considered as contiguous.

For example in the embodiment of FIG. 5, the series resistance increaseswith increasing longitudinal length L of the gate electrode anddecreases with decreasing length L. Thus, an FET of a large output powercan be formed by connecting a large number of such channels.

FIG. 7 shows an embodiment of a large output FET along the above line.

Alternatively, a large output FET having a planar structure as shown inFIG. 8 may be formed. In this case, the distance 2a between the adjacentgates is also arranged considering the impurity concentration so thatthe current channel is interrupted by the contiguous depletion layers.The gates and the sources are respectively connected in parallel for alarge power transistor.

Various alterations and modifications are possible within the spirit andscope of the present invention.

If the impurity concentration in the channel region is not uniform dueto the employment of a diffusion process, etc., the calculation of theheight of a depletion layer becomes complicated, but a value three timesas large as the calculated value on the basis of the perfect ionizationassumption also holds for the actual situation.

The present invention is not limited to junction-gate type FET's, but isalso applicable to MOS FET's. The gist of the present invention lies inthe depletion layers contiguous to each other. In a MOS FET, a spacecharge region is usually formed under an oxide film beneath the gateelectrode. The dimension of the space charge region differs according tothe properties of the oxide film but can be given by the Debye lengthwhich is dependent on the impurity concentration in the substrate. Thus,structures in which depletion layers touch each other even in theabsence of a gate voltage can also be realized in MOS structure byutilizing the internal potential at an insulator-semi-conductor contactcorresponding to the barrier potential at a junction.

FIGS. 9, 10, and 11 show embodiments of MOS FET's according to theinvention. In FIG. 9 a source and a drain electrode is formed on theopposite surfaces and a gate electrode is formed around the source toeffectively extend the depletion layer. The radius of the gate electrodeis selected less than the Debye length so that the current channel fromthe source electrode is closed by the depletion layer even in theabsence of a gate voltage. FIG. 10 shows an embodiment in which anelectrically isolated region is formed in one surface of a semiconductorsubstrate, and a source, an annular gate and an annular drain electrodeare formed on said region.

FIG. 11 shows another embodiment which is intended to provide a highoutput power by alternatively forming source and drain electrodesrespectively connected in parallel.

In the above embodiments, the shape of the source and/or drain and/orgate electrode may be rectangular or comb form. The gate electrodes areinsulated from the semi-conductor substrate by an insulator film such asan SiO₂ film.

The present invention is applied to silicon elements in the aboveembodiments but is also applicable to other semiconductor materials suchas GaAs. Further, with the use of a hetero junction, a space chargedregion not only due to the carrier concentration but also due to thedifference in the band structures can be utilized.

The present invention is described on various structures, but is mosteffective to those having a reduced series resistance to have a smalloutput resistance. If such elements are assembled in an integratedcircuit, there can be provided superior switching characteristics whichare made more effective by the smallness of the accompanyingcapacitances.

When the gate-to-gate distance is further reduced, the standing-up pointof the drain current shifts to higher drain voltage side and suitablecircuit designs based on the thus obtained characteristics are possible.Therefore, this invention gives the upper limit for the gate-to-gatedistance.

We claim:
 1. A field effect semiconductor device capable of exhibitingunsaturable drain voltage versus drain current characteristicscomprising:a first and second spaced gate region formed of a relativelyhigh impurity doped semiconductor material and having a firstconductivity type; a semiconductor region located adjacent to said firstand second spaced regions and having an opposite conductivity type, said.[.second.]. .Iadd.semiconductor .Iaddend.region being formed of asubstantially intrinsic semiconductor material of a low carrierconcentration, said semiconductor region having a portion forming acurrent channel between said first and second gate regions, said channelincluding the semiconductor region disposed between respective junctionsformed with said first and second gate regions defining the sides ofsaid channels and including a depletion layer incident to each of saidjunctions, said depletion layers being contiguous or overlapping eachother to achieve a pinch-off condition within said channel in theabsence of a reverse bias voltage applied to said first and second gateregions; a source region located along said channel for supplying acurrent thereto; a drain region spaced from said source region alongsaid channel for providing an output current, said source region anddrain region comprising semiconductor regions having the sameconductivity type as said channel region; gate biasing means forapplying a reverse bias voltage to said first and second gate regions toincrease the effective length of the overlapping depletion layers alongsaid current channel with an increase in magnitude of the appliedreverse bias voltage to thereby determine a threshold drain voltage,wherein the application of a drain voltage greater than said thresholdvoltage allows the carriers from the source region to travel toward saiddrain region in the depletion layer existing along the current channelin the same manner as that exhibited by a triode vacuum tube.
 2. Thefield effect semiconductor device of claim 1, in which the extent of thedepth of said depletion layers is determined by the contact potential atsaid junction and by the impurity concentration of the semiconductormaterial of the channel region, wherein the gate-to-gate distance isdetermined.
 3. The field effect semiconductor device of claim 1, inwhich the output current at said drain region exhibits an unsaturatednon-linear characteristic with respect to the applied drain voltage whensaid drain voltage is above a threshold determined by a given gate biasvoltage.
 4. The field effect semiconductor device of claim 1, in whichsaid channel constituting the semiconductor region is formed of a plateelongated in the source-to-drain direction, and said first and secondgate regions are formed on the two principal surfaces of said platesandwiching therebetween said current channel, the depletion layersextending from said gates and contacting or overlapping each other. 5.The field effect semiconductor device of claim 4, in which each of saidgate electrodes has a dimension in the longitudinal direction along saidcurrent channel small enough to reduce the series resistance of thechannel.
 6. The field effect semiconductor device of claim 1, in whichsaid source and drain regions and said gate regions are disposed on onesurface of the semiconductor material constituting the current channel.7. The field effect semiconductor device of claim 1, in which saidchannel constituting semiconductor material is silicon having animpurity concentration below the order of 10¹⁵ /cm³.
 8. The field effectsemiconductor device of claim 4, in which said current channel betweenthe gate regions has a diametrical dimension of at most three times thetotal width of the total depletion layers calculated from the assumptionof perfect ionization in the depletion layers.
 9. A field effecttransistor according to claim .[.1.]. .Iadd.19.Iaddend., wherein saidsemiconductor substrate is cylindrical and the gate electrode has ahollow cylindrical shape formed on the side surface of said cylindricalsubstrate surrounding the current channel extending therewithin.
 10. Afield effect transistor according to claim .[.1.]. .Iadd.19.Iaddend.,wherein said gate electrode is annular and surrounds the sourceelectrode. .[.11. A field effect transistor according to claim 1,wherein said semiconductor substrate is cylindrical and said gateelectrode is formed on an intermediate portion of the side surface ofsaid cylinder..].
 12. A field effect transistor according to claim.[.1.]. .Iadd.19 .Iaddend.wherein a plurality of said gate regions areformed in and traversing the current channel. .Iadd.
 13. A field effectsemiconductor comprisinga semiconductor region formed of a substantiallyintrinsic semiconductor material having a low carrier concentration, atleast one source region of a predetermined conductivity type adjacent tosaid semiconductor region, at least one drain region of saidpredetermined conductivity type adjacent to said semiconductor region,removed from said source region, thereby constituting in saidsemiconductor region a current path from said source to said drain, andat least one gate structure connected to said semiconductor region toform a depletion layer in said semiconductor region extending from saidgate which substantially occupies a whole cross-section of said currentpath in the absence of a gate voltage, said depletion layer being ofminimum effective size in the absence of said gate voltage..Iaddend..Iadd.
 14. A field effect semiconductor device comprisingasemiconductor region formed of a substantially intrinsic semiconductormaterial having a low carrier concentration, at least one source regionadjacent to said semiconductor region, at least one drain regionadjacent to said semiconductor region, removed from said source region,thereby constituting in said semiconductor region a current path fromsaid source to said drain, said source and drain regions being heavilydoped and of the same conductivity type, and at least one gate structureconnected to said semiconductor region to form a depletion layer in saidsemiconductor region extending from said gate which substantiallyoccupies a whole cross-section of said current path in the absence of agate voltage, wherein the application of a drain voltage greater than athreshold voltage forces the carriers from the source to travel towardsaid drain along said current path through said depletion layer tothereby provide a current-voltage characteristic similar to that of avacuum tube triode. .Iaddend. .Iadd.
 15. A field effect semiconductordevice comprisinga semiconductor region formed of a substantiallyintrinsic semiconductor material having a low carrier concentration,said carrier concentration being less than 10¹⁵ /cm³, at least onesource adjacent to said semiconductor region, at least one drainadjacent to said semiconductor region removed from said source region,thereby constituting in said semiconductor region a current path fromsaid source to said drain, said source and drain regions being of thesame conductivity type, and at least one gate connected to saidsemiconductor region to form a depletion layer in said semiconductorregion extending from said gate which substantially occupies a wholecross-section of said current path in the absence of a gate voltage,wherein upon the application of a reverse bias gate voltage, a thresholdvoltage is defined above which a drain voltage forces carriers from thesource toward said drain through said depletion layer occupying a wholecross-section of said current path to thereby provide a current-voltagecharacteristic similar to that of a vacuum triode. .Iaddend..Iadd.
 16. Afield effect semiconductor device capable of exhibiting unsaturabledrain voltage versus drain current characteristics comprising: asubstantially intrinsic semiconductor region; source and drainsemiconductor regions, said source and drain regions being highly dopedand of the same conductivity type, and being disposed contiguous to saidintrinsic region, said source and drain regions defining a current paththerebetween through a portion of said intrinsic region; and gate meansfor controlling current through said current path in accordance with agate voltage applied thereto, carriers flowing along said path from saidsource to said drain when the voltage at said drain exceeds apredetermined threshold value; said gate means including contactpotential producing means contiguous to said intrinsic region forgenerating, in the absence of a gate voltage applied to said gate means,a potential at the junction of said potential producing means with saidintrinsic region, said potential producing a depletion layer extendingacross substantially an entire cross-section of said current path suchthat said carriers flowing along said current path must pass throughsaid depletion layer, said depletion layer increasing in effective sizein response to increasing magnitude of said applied gate voltage todetermine thereby said threshold drain voltage value. .Iaddend..Iadd.17. The device of claim 16 wherein said gate means comprises: a layer ofinsulator material, one surface thereof adjacent said intrinsic region;and a metallic electrode disposed on the surface of said insulator layeropposite said one surface. .Iaddend. .Iadd.
 18. A field effectsemiconductor device capable of exhibiting unsaturable drain voltageversus drain current characteristics comprising: a gate region formed ofa relatively high impurity doped semiconductor material and having afirst conductivity type; a semiconductor region located adjacent to saidgate region and having a second conductivity type opposite said firstconductivity type, said semiconductor region being formed of asubstantially intrinsic semiconductor material of a low carrierconcentration; a source region formed of a relatively high impuritydoped semiconductor material and connected to said semiconductor region;a drain region formed of a relatively high impurity doped semiconductormaterial and connected to said semiconductor region; said source anddrain regions defining a current path therebetween through saidsemiconductor region, current flowing from said source to said drainalong said current path in response to a drain voltage in excess of apredetermined threshold voltage; said semiconductor region including adepletion layer incident to said gate region, said depletion layerforming a pinched-off area within said path in the absence of a reversebias voltage applied to said gate region; means for applying a reversebias voltage to said gate region to increase the effective length of thedepletion layer forming said pinched-off area along said current path inaccordance with an increase in magnitude of the applied reverse biasvoltage, to define thereby said threshold drain voltage whereby theapplication of a drain voltage greater than said threshold voltageforces carriers from the source region to travel toward said drainregion through said depletion layer. .Iaddend..Iadd.
 19. A field effectsemiconductor device capable of exhibiting unsaturable drain voltageversus drain current characteristics comprising:at least one gate regionformed of a relatively high impurity doped semiconductor material havinga first conductivity type; a semiconductor region located adjacent tosaid gate region and having a second conductivity type which is oppositeto said first conductivity type, said semiconductor regions being formedof a substantially intrinsic semiconductor material of a low carrierconcentration; a source region formed of a relatively high impuritydoped semiconductor material and connected to said semiconductor region;a drain region formed of a relatively high impurity doped semiconductormaterial and connected to said semiconductor region; said source anddrain regions defining a current path therebetween through saidsemiconductor region, current flowing from said source to said drainalong said current path when the voltage at said drain region exceeds athreshold drain voltage; said semiconductor region having a portionforming a current path, said path including the semiconductor regiondisposed between the junction formed with said at least one gate regionand including a depletion layer incident to said junction, saiddepletion layer forming a pinched-off area within said current path inthe absence of a reverse bias voltage applied to said gate region; andgate biasing means for applying a reverse bias voltage to said at leastone gate region to increase the effective length of said depletion layeralong said current path in accordance with an increase in magnitude ofthe applied reverse bias voltage, to determine thereby said thresholddrain voltage, whereby the application of a drain voltage greater thansaid threshold voltage forces carriers from the source region to traveltoward said drain region through said depletion layer in the same manneras that exhibited by a triode vacuum tube. .Iaddend.